The present invention relates to an Error Detection and Correction (EDAC) apparatus, and more particularly, to an EDAC apparatus for use with a memory unit utilizing BY-4 memory chips.
Previous memory architectures are structured to utilize BY-1 memory devices, e.g., Random Access Memory (RAM) or Dynamic Random Access Memory (DRAM), there generally being no need to protect any more than a 1 bit failure or a 1 bit soft error at a time for such devices. (BY-1 memory devices include those devices well known in the art such as 4K BY-1, 16K BY-1or 64K BY-1 RAM organization, also denoted as 4K.times.1, 16K.times.1, or 64K.times.1, respectively.) Thus, for a 32 bit word memory, 32 BY-1 memory chips are utilized, and if a 1K word memory unit having 32 bits per word is desired, 32 chips of a 1K BY-1 are utilized.
As a result of memory density increase, BY-4 memory devices (or chips) have been developed which are more economical and are finding widespread acceptance and usage in current systems. Thus, it can be seen for the same 1K word memory unit, having 32 bits per word, 8 memory chips of a 1K BY-4 are utilized.
There currently exists a variety of EDAC schemes which can detect and correct 1 bit errors in a word fetched from the memory unit. Some EDAC schemes can detect all two bit errors in a word and some three and four bit word errors.
A need exists to detect all two bit word errors, and to detect all two, three, and four bit errors of the same chip of a BY-4 memory device. The present invention provides an apparatus which detects and corrects all one bit errors, detects all two bit word errors of a computer word, and detects all two, three, and four bit errors on the same chip.